1. Field of the Disclosure
The disclosure relates to a method of making a semiconductor device. More particularly, the disclosure relates to a method of making a semiconductor device, which can simplify control of an etch bias and improve the process margin of patterns by preparing dummy patterns at a lower-density portion among parts of relatively different densities of patterns to be formed in a photolithography process, the dummy patterns having the same size as the pattern desired to be formed, not over active areas, but over adjacent inactive areas.
2. Description of the Related Technology
Generally, a process of manufacturing a semiconductor device includes the step of manufacturing a pattern of a desired shape by depositing a specific thin film and selectively etching parts of the thin film through a photolithography process. In this step, the aforementioned pattern may have a high-density pattern area in which a great number of repetitive patterns are located in a narrow region, a low-density pattern area in which a small number of patterns are located in a wide region, and an intermediate-density pattern area between the high-density and low-density areas.
FIG. 1 is a plan view for explaining pattern areas having different densities of a semiconductor device in general. Herein, reference numeral 1 denotes a gate pattern, which is a main pattern, and reference numerals 2 and 3 denote an active area and a bit-line contact, respectively. Further, the letter A denotes a high-density pattern area, the letter B denotes an intermediate-density pattern area, and the letter C denotes a low-density pattern area.
The low-density pattern area C is lowered in its process margin in the photolithography process compared to the high-density pattern area A. To compensate for this, a process using a smaller wavelength and various RETs (Resolution Enhancement Technologies) is used, but the low-density pattern area C causes a sharp reduction in the margin of depth of focus process. Additionally, because, in an etching process for the pattern of the low-density area C, there is a relatively large bias compared to pattern A of the high-density area exists, a light exposure process has to be implemented at a smaller process margin. Furthermore, because the profile of the photoresist is deteriorated after light exposure, the uniformity of the critical regions is lowered to a large extent.
Conventionally, a exposure mask with an assist feature has been employed to improve the uniformity margin of critical regions for the low-density pattern area C. However, the assist feature does not actually form a pattern on a wafer, and affords only a small improvement in the depth of focus margin. Thus, it does not help to control etch bias or enhance the uniformity of critical regions.
FIG. 2 illustrates a conventional example of the formation of a low-density pattern area utilizing an assist feature. As illustrated therein, there is prepared an assist feature 4 for transmitting light onto the side parts of a gate pattern 1. Such an assist feature 4 is very small in width as compared to the gate pattern 1, the main pattern, and is shown only on an exposure mask, but does not actually form a pattern on a wafer.
FIG. 3 graphically illustrates the depth of focus process margin of each of the patterns by density so that the process utilizing the assist feature 4 may be compared with the process not utilizing the assist feature in terms of depth of the focus process margin. It can be seen that the depth of the focus process margin of the low-density pattern area in the process utilizing the assist feature 4 is enhanced compared to the process not utilizing the assist feature 4, but needs still more improvement as compared to the high-density pattern area and the intermediate-density pattern area.